R&D Engineer at ASYGN
Stephane Breysse is a(n) R&D Engineer working at ASYGN.
Get Stephane Breysse's email for freeName | Position | Contacts | ||
---|---|---|---|---|
JP | Jerome Pons | Senior Analog IC Design EngineerASYGN | @asygn.com+33 4 | Get contact |
BM | Ben Maryam | Hardware design engineerASYGN | @asygn.com+33 4 | Get contact |
GF | Gael Ferard | Embedded Software EngineerASYGN | @asygn.com+33 4 | Get contact |
TP | Tanguy Pepin | Back-End/Analog IC Layout TechnicianASYGN | @asygn.com+33 4 | Get contact |
AD | Alessandro Dezzani | Senior Analog-RF EngineerASYGN | @asygn.com+33 4 | Get contact |
AV | Adrien Vialletelle | Junior Application EngineerASYGN | @asygn.com+33 4 | Get contact |
CB | Christophe Blanc | System design managerASYGN | @asygn.com+33 4 | Get contact |
ND | Nicolas Delorme | CTOASYGN | @asygn.com+33 4 | Get contact |
JG | Jose Guerra | Analog/RF designerASYGN | @asygn.com+33 4 | Get contact |
Name | Position | Contacts | ||
---|---|---|---|---|
PM | Patrick Maitre | R&D Engineer, Silicon photonicsSTMicroelectronics | @st.com+41 2 | Get contact |
OK | Osama Khalil | R&D EngineerQuantumClean | @qua….com(215) | Get contact |
KB | Kanika Bhatia | Test R&D EngineerIntel Corporation | @intel.com(408) | Get contact |
MN | Minghao Ni | R&D engineerLattice Semiconductor | @lat….com(503) | Get contact |
JF | Julien Ferrand | R&D engineer - High-k and EpitaxySTMicroelectronics | @st.com+41 2 | Get contact |
GA | Gregory Avenier | Senior R&D engineer and Project leader: BiCMOS Technologies DevelopmentSTMicroelectronics | @st.com+41 2 | Get contact |
LB | Laurene Babaud | R&D EngineerSTMicroelectronics | @st.com+41 2 | Get contact |
MK | Matjaz Kolaric | R&D engineerSTMicroelectronics | @st.com+41 2 | Get contact |
YL | Yingzhuo Liu | R&D engineerASM | @asm.com+31 8 | Get contact |
HY | Hai Yang | R&D engineerASM | @asm.com+31 8 | Get contact |