R&D Engineer at ASYGN
Stephane Breysse is a(n) R&D Engineer working at ASYGN.
Get Stephane Breysse's email for freeName | Position | Contacts | ||
---|---|---|---|---|
JP | Jerome Pons | Senior Analog IC Design EngineerASYGN | @asygn.com+33 4 | Get contact |
BM | Ben Maryam | Hardware design engineerASYGN | @asygn.com+33 4 | Get contact |
GF | Gael Ferard | Embedded Software EngineerASYGN | @asygn.com+33 4 | Get contact |
TP | Tanguy Pepin | Back-End/Analog IC Layout TechnicianASYGN | @asygn.com+33 4 | Get contact |
AD | Alessandro Dezzani | Senior Analog-RF EngineerASYGN | @asygn.com+33 4 | Get contact |
AV | Adrien Vialletelle | Junior Application EngineerASYGN | @asygn.com+33 4 | Get contact |
CB | Christophe Blanc | System design managerASYGN | @asygn.com+33 4 | Get contact |
ND | Nicolas Delorme | CTOASYGN | @asygn.com+33 4 | Get contact |
JG | Jose Guerra | Analog/RF designerASYGN | @asygn.com+33 4 | Get contact |
Name | Position | Contacts | ||
---|---|---|---|---|
PM | Patrick Maitre | R&D Engineer, Silicon photonicsSTMicroelectronics | @st.com+41 2 | Get contact |
LI | Lisa Irimata | Packing R&D EngineerIntel Corporation | @intel.com(408) | Get contact |
SS | Shaariq Shaikh | Test R&D EngineerIntel Corporation | @intel.com(408) | Get contact |
NR | Nick Ross | Sr. Packaging R&D EngineerIntel Corporation | @intel.com(408) | Get contact |
YL | Yingzhuo Liu | R&D engineerASM | @asm.com+31 8 | Get contact |
HY | Hai Yang | R&D engineerASM | @asm.com+31 8 | Get contact |
NB | Nitesh Barwade | R&D Engineer IC Design llLSI, an Avago Technologies Company | @lsi.com(408) | Get contact |
SD | Sean Devlin | IC Packaging R&D EngineerIntel Corporation | @intel.com(408) | Get contact |
YG | Yang Guo | Packaging R&D EngineerIntel Corporation | @intel.com(408) | Get contact |
ST | Sridutt Tummalapalli | Test R&D EngineerIntel Corporation | @intel.com(408) | Get contact |