Design Engineer at System-on-Chip Technologies
Roman Sanine is a(n) Design Engineer working at System-on-Chip Technologies.
Get Roman Sanine's email for freeName | Position | Contacts | ||
---|---|---|---|---|
ST | Soc Technologies | CompanySystem-on-Chip Technologies | @soc….com(519) | Get contact |
CM | Cornel Mercea | PCB Design EngineerSystem-on-Chip Technologies | @soc….com(519) | Get contact |
RY | Robert Young | Vice President Sales & MarketingSystem-on-Chip Technologies | @soc….com(519) | Get contact |
GC | Gabriel Carle | Senior Design EngineerSystem-on-Chip Technologies | @soc….com(519) | Get contact |
SS | Shaowen Song | President & CTOSystem-on-Chip Technologies | @soc….com(519) | Get contact |
MF | Maria Fedorov | Project ManagerSystem-on-Chip Technologies | @soc….com(519) | Get contact |
WL | Wen Li | Senior Design EngineerSystem-on-Chip Technologies | @soc….com(519) | Get contact |
Name | Position | Contacts | ||
---|---|---|---|---|
JS | Jun Sagun | Senior PSU Design EngineerHuntkey | @huntkey.net(400) | Get contact |
WT | Wayne Thompson | Design EngineerRTS | @rts…s.uk+44 7 | Get contact |
PC | Pietro Cusmano | Senior ASIC Design EngineerNVIDIA | @nvidia.com(408) | Get contact |
JS | John Shen | Software Design EngineerInventec | @inv….com(408) | Get contact |
AS | Ariel Sorochkin | Senior Hardware Design EngineerSR Research Ltd. | @sr-….com(613) | Get contact |
TN | Talha Nadat | Hardware Design EngineerNallatech | @nal….com+44 1 | Get contact |
SS | Siddharth Sharma | Design Engineer, Deep Learning HW/SW Co-designNVXL Technology, Inc. | @nvx….com | Get contact |
TH | Tom Hickok | ASIC Design EngineerHGST, a Western Digital brand | @hgst.com(800) | Get contact |
CD | Chris Dudley | Principal ASIC Design EngineerHGST, a Western Digital brand | @hgst.com(800) | Get contact |
AC | Ashwin Chiluka | Principal Hardware Design EngineerHGST, a Western Digital brand | @hgst.com(800) | Get contact |