Verification Engineer at Avago Technologies
Chao Qin is a(n) Verification Engineer working at Avago Technologies.
Get Chao Qin's email for freeName | Position | Contacts | ||
---|---|---|---|---|
HB | Haijiao Bian | EngineerAvago Technologies | @ava….com(408) | Get contact |
VM | Vijay Mehere | R and D EngineerAvago Technologies | @ava….com(408) | Get contact |
RB | Roswitha Blischke | R&D TechnicanAvago Technologies | @ava….com(408) | Get contact |
CL | Chi Law | Design EngineerAvago Technologies | @ava….com(408) | Get contact |
CC | Choon-Len Chong | @ava….com(408) | Get contact | |
SC | Sin Cheah | Supply Chain ManagerAvago Technologies | @ava….com(408) | Get contact |
HP | Hooi Pang | Process EngineerAvago Technologies | @ava….com(408) | Get contact |
MS | Meng Shie | @ava….com(408) | Get contact | |
AS | Anuj Soni | Staff engineerAvago Technologies | @ava….com(408) | Get contact |
YF | Yin Fong | Senior RFIC Design EngineerAvago Technologies | @ava….com(408) | Get contact |
Name | Position | Contacts | ||
---|---|---|---|---|
GF | Goure Franck | RTL verification engineerSTMicroelectronics | @st.com+41 2 | Get contact |
MP | Michael Pertin | IP verification engineerSTMicroelectronics | @st.com+41 2 | Get contact |
OB | Oscar Belotti | Mixed signal designer/verification engineerSTMicroelectronics | @st.com+41 2 | Get contact |
OC | Oxana Chich | STNoC Verification EngineerSTMicroelectronics | @st.com+41 2 | Get contact |
AG | Arpit Gupta | Design Verification EngineerSTMicroelectronics | @st.com+41 2 | Get contact |
MC | Marc Cardineau | Design Verification EngineerSTMicroelectronics | @st.com+41 2 | Get contact |
LG | Lovekesh Gupta | Sr. Verification EngineerSTMicroelectronics | @st.com+41 2 | Get contact |
FR | Francois Ravatin | Senior AMS Verification EngineerSTMicroelectronics | @st.com+41 2 | Get contact |
AV | Akos Varga | Digital Design and Functional Verification EngineerFrobas d.o.o. | @frobas.com | Get contact |
MR | Mohan Rao | SMTS Verification EngineerRambus | @rambus.com+44 1 | Get contact |